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Serial Quad I/O (SQI) Flash Memory
A Microchip Technology Company
SST26VF016 / SST26VF032
Data Sheet
Read Block Index (Read BI)
The Read Block Index (Read BI) instruction increments the address counter a specified number of 64
KByte blocks. To execute a Read BI operation the host drives CE# low, then sends the Read BI com-
mand cycle (10H), one address cycle, and two dummy cycles. Each cycle is two nibbles (clocks) long,
most significant nibble first.
The address cycle contains a two’s complement number specifying the number of blocks and the
direction the address pointer will jump. The least significant address bits, A15:A0, do not change.
After the dummy cycle, the device outputs data on the falling edge of the SCK signal starting from the
specified address location.
JEDEC-ID Read (SPI Protocol)
Using traditional SPI protocol, the JEDEC-ID Read instruction identifies the device as SST26VF016/
032 and the manufacturer as SST. To execute a JECEC-ID operation the host drives CE# low then
sends the JEDEC-ID command cycle (9FH). For SPI modes, each cycle is eight bits (clocks) long,
most significant bit first.
Immediately following the command cycle the device outputs data on the falling edge of the SCK sig-
nal. The data output stream is continuous until terminated by a low-to-high transition on CE#. The
device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure
13 for instruction sequence.
Table 6: Device ID Data Output
Device ID
Product
SST26VF016
SST26VF032
Manufacturer ID (Byte 1)
BFH
BFH
Device Type (Byte 2)
26H
26H
Device ID (Byte 3)
01H
02H
T6.1
25017
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK
SI
MODE 0
9F
SO
HIGH IMPEDANCE
BF
26
Device ID
MSB
MSB
1359 F38.0
Note: SIO2 and SIO3 must be driven V IH
Figure 13: JEDEC-ID Sequence (SPI Mode)
?2011 Silicon Storage Technology, Inc.
18
DS-25017A
04/11
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